1. Field of the Invention
The present invention relates to the field of interface bridges between bus domains. Specifically, the present invention relates to bridging a processor bus domain to a second bus domain.
2. Related Art
The prior art configuration of FIG. 1 shows a host computer""s general Central Processing Unit (CPU) 100 interfaced to a Peripheral Component Interconnect (PCI) device 104 via a Northbridge integrated circuit device 102. The Northbridge device is commercially available for that use. Similarly, the Southbridge device 106 is also readily available for purposes of interfacing a general purpose CPU 100 to an ISA device 108.
Unlike commercially available CPUs, the Advanced RISC Machine (ARM) processor is a special purpose, user-customizable RISC processor which is very well suited to processor-intensive functions, such as handwriting recognition and other real-time digital signal processing applications for data and voice communications. With ARM""s small 32 bit RISC CPUs, integrated, high performance designs can be custom-developed for relatively very fast time-to-market and low product development costs.
PCI-based computer peripheral devices are used extensively in host computer systems and are readily available commercially. One reason why the ARM processor has not been combined with a PCI device is due to the fact that host computers use general purpose CPUs, which can be interfaced to PCI devices using the Northbridge solution.
Embedding an ARM processor for a specialized subsystem function, such as within a network adapter interface card, can significantly improve the overall host system performance since it lessens the need to use the host CPU for the subsystem networking functions. So to the extent that an embedded processor can perform the network subsystem processor functions, it frees up the host CPU for other higher priority processing tasks. However, use of an ARM processor embedded within the network adapter subsystem can only be advantageous if the ARM processor can be interfaced to communicate with a PCI-based host CPU and other PCI peripheral devices through the PCI bus.
One interface bus developed for the ARM processor is the Advanced Microcontroller Bus Architecture (AMBA) which defines the Advanced System Bus (ASB). However, the AMBA ASB bus and the PCI bus operate at different clock frequencies and have different signaling schemes for data communication. Unlike the Northbridge device which exists to interface between general purpose CPUs and the PCI bus, there are no known devices for bridging between the ARM processor and a PCI interface bus.
The present invention provides a method and apparatus to bridge between the PCI bus and a RISC processor interface bus. In one embodiment, the present invention is a single-ASIC implementation rather than a design using multiple discrete circuit components. The invention incorporates a method and apparatus that will minimize subsystem latencies and inefficiencies in order to maximize data throughput and system performance. In yet another embodiment, the RISC processor interface bus is the AMBA ASB bus. The invention further provides an Advanced RISC Machine interface bus unit which uses an improved clock crossing handshake mechanism that can support a range of clock frequencies on the AMBA ASB bus.
The invention comprises a RISC processor bus coupled to a RISC processor interface unit for generating memory access requests and for generating requests over a Peripheral Component Interconnect bus. A memory interface unit is coupled to a memory unit and is for responding to memory access requests from a Peripheral Component Interconnect interface unit which is coupled to a Peripheral Component Interconnect bus. The Peripheral Component Interconnect interface unit is for communicating with a PCI device. An internal bus is coupled to the RISC processor interface unit, the memory interface unit and said Peripheral Component Interconnect interface unit. A RISC processor is coupled to the RISC processor bus, the RISC processor for communicating with the memory unit and with the Peripheral Component Interconnect device. The RISC processor interface unit operates at a first clock frequency, and the Peripheral Component Interconnect interface unit operates at a second clock frequency.
Specifically, an embodiment of the present invention includes an interface circuit comprising: a RISC processor bus; a RISC processor interface unit coupled to the RISC processor bus for generating memory access requests and for generating requests over a Peripheral Component Interconnect bus; a memory unit; a memory interface unit coupled to the memory unit and for responding to memory access requests to the memory unit; a Peripheral Component Interconnect interface unit coupled to a Peripheral Component Interconnect bus, the Peripheral Component Interconnect interface unit for communicating with a Peripheral Component Interconnect device; an internal bus coupled to the RISC processor interface unit, the memory interface unit and the Peripheral Component Interconnect interface unit; and a RISC processor coupled to the RISC processor bus, the RISC processor for communicating with the memory unit and with the Peripheral Component Interconnect device, wherein the RISC processor interface unit operates at a first clock frequency and wherein the Peripheral Component Interconnect interface unit operates at a second clock frequency.